Avago Technologies LSI53C1010R - Manual (Page 32)

2-2 Functional Description
Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
Figure 2.1 LSI53C1010R Block Diagram
The LSI53C1010R has two wide Ultra160 SCSI channels in a single
package. Each SCSI channel (A and B) incorporates an independent
DMA FIFO and a separate internal 8 Kbyte SCRIPTS RAM.
2.1 PCI Functional Description
The LSI53C1010R implements two PCI to Wide Ultra160 SCSI
controllers in a single package. This configuration presents only one load
to the PCI bus and uses only one REQ/ - GNT/ pair for PCI bus
arbitration. Separate interrupt signals are generated for SCSI Function A
and SCSI Function B.
8 Kbyte
SCRIPTS RAM
8 Dword SCRIPTS
Prefetch Buffer
Oper
ating
Registers
SCSI SCRIPTS
Processor
920 Byte
DMA FIFO
SCSI FIFO and SCSI Control Block
Universal TolerANT
Drivers and Receivers
64-Bit PCI Interface, PCI Configuration Registers (2 Sets)
Wide Ultra160 SCSI Channel
Ser
ial EEPR
OM Controller
and A
utoconfigur
ation
R
OM/Flash Memor
y Control
Local
Bus
Memory
SCSI SCRIPTS
Processor
944 Byte
DMA FIFO
SCSI FIFO and SCSI Control Block
Universal TolerANT
Drivers and Receivers
Wide Ultra160 SCSI Channel
Oper
ating
Registers
PCI Bus
SCSI Function B
Wide Ultra160
SCSI Bus
SCSI Function A
Wide Ultra160
SCSI Bus
JTAG
ROM/Flash
Memory
Bus
2-Wire Serial
EEPROM Bus
(Function A)
2-Wire Serial
EEPROM Bus
(Function B)
JTAG
Bus
8 Kbyte
SCRIPTS RAM
8 Dword SCRIPTS
Prefetch Buffer