Avago Technologies LSI53C1010R - Manual (Page 245)

SCSI Shadow Registers 4-127
Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
Register: 0x43
Shadowed SCSI Interrupt Status One (SIST1)
Read Only
This register contains the individual status bits that cause an SGE SCSI
interrupt. These bits correspond to the SGE conditions described in the
SIST0 register description. Unlike the other registers in the device, these
bits must be set to one to clear the condition. This register is shadowed
behind the
SCSI Interrupt Status One (SIST1) register. It can be
accessed by setting bit 7, the Enable Shadowed SGE Register (ShSGE)
bit, in the
Chip Control Two (CCNTL2) register.
R Reserved [7:6]
PNCRC Pad Request with no CRC Request Following 5
FCRC Force CRC 4
DTST Switch from DT to ST timings during a transfer 3
NFCRC Phase Change with no final CRC Request 2
MCRC Multiple CRC Requests with the same offset 1
R Reserved 0
7 6 5 4 3 2 1 0
R PNCRC FCRC DTST NFCRC MCRC R
0 0 0 0 0 0 0 0