Avago Technologies LSI53C1010R - Manual (Page 27)

Summary of LSI53C1010R Benefits 1-9
Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
– Supports dual address cycle (DAC) generation for all SCRIPTS
– Presents a single electrical load to the PCI Bus (True PCI
Multifunction Device)
•
Bursts 4/8, 8/16, 16/32, 32/64, or 64/128 Qword/Dword transfers
across the PCI bus.
•
Supports 32-bit or 64-bit word data bursts with variable burst lengths.
•
Prefetches up to 8 Dwords of SCRIPTS instructions.
•
Bursts SCRIPTS opcode fetches across the PCI bus.
•
Performs zero wait-state bus master data bursts up to 528 Mbytes/s
(@ 66 MHz).
•
Supports PCI Cache Line Size (CLS) register.
•
Supports PCI Write and Invalidate, Read Line, and Read Multiple
commands.
•
Complies with PCI Bus Power Management Specification Rev 1.1.
•
Complies with PC99.
1.6.3 Integration
The following features ease integration of the LSI53C1010R into a
system.
•
Dual channel Ultra160 SCSI PCI multifunction controller.
•
Integrated LVD transceivers.
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Full 32-bit or 64-bit PCI DMA bus master.
•
Memory-to-Memory Move instructions allow use as a third-party PCI
bus DMA controller.
•
Integrated SCRIPTS processor.
1.6.4 Ease of Use
The following features of the LSI53C1010R make the device user friendly.
•
The LSI53C1010R is pin compatible with the LSI53C1030 PCI to
Dual Channel Ultra320 SCSI Multifunction Controller.
•
Up to 1 Mbyte of add-in memory support for BIOS and SCRIPTS
storage.