Avago Technologies LSI53C1010R - Manual (Page 385)

Index IX-9
Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
16 Kbyte
200 ns memory B-9
512 Kbyte
150 ns memory B-12
64 Kbyte
150 ns memory B-10
control signals 3-7
parallel ROM 2-59
internal
arbiter 2-11
pull-ups and pull-downs 3-4
RAM 2-20
SCRIPTS RAM 2-20
interrupt
A 3-9
acknowledge command 2-5
B 3-9
fatal 2-48
flushing 4-51
halting 2-51
handling 2-45
hardware 2-46
instruction 5-31
INTC/ 2-53
INTD/ 2-53
line register 4-16
mask bits 4-66 , 4-70
masking 2-49
nonfatal 2-48
on the fly 5-33
on the fly (INTF) 4-50
output 6-12
pin (IP[7:0]) 4-16
polling 2-46
registers 2-46
DIEN 2-48
DSTAT 2-48
ISTAT 2-46
SIEN0 2-48
SIEN1 2-48
SIST0 2-47
SIST1 2-47
request 2-46
routing mode (IRM[1:0]) 4-87
sample interrupt service routine 2-52
SCRIPT interrupt instruction received 4-42
signals 3-9
single step 4-42
stacked 2-50
status one (ISTAT1) 2-46 , 4-51
status zero (ISTAT0) 2-46 , 4-48
interrupt-on-the-fly instruction 5-31
interrupts 2-48 , 2-53
nonfatal 2-48
IRDY/ 3-7
IRQ mode (IRQM) 4-68
issuing cache commands 2-13
ISTAT 2-46
J
JTAG
boundary scan testing 2-33
signals 3-19
jump
address 5-35
call a relative address 5-32
call an absolute address 5-32
control (PMJCTL) 4-93
if true/false 5-33
instruction 5-29
JUMP64 address 5-35
L
last disconnect (LDSC) 4-47
latched SCSI parity 4-45
for SD[15:8] (SPL1) 4-47
latency 2-10
timer (LT[7:0]) 4-8
LED 2-21
LED_CNTL (LEDC) 4-79
little endian 2-18
load and store
instructions 2-33 , 5-39
prefetch unit and store instructions 2-32
load/store 5-41
lost arbitration (LOA) 4-44
low voltage differentia, See LVD Link 2-39
LSI53C1010R
register map A-1 , A-3
LSI53C700 family compatibility 4-69
LVD 2-39
driver SCSI signals 6-3
receiver SCSI signals 6-3
LVD Link 1-2 , 1-5 , 2-39
benefits 1-5
M
M66EN 3-5
MAD bus programming 3-22
MAD[0] 3-23
MAD[3:1] 3-22
MAD[3:1] pin decoding 3-23
MAD[4] 3-22
MAD[5] 3-22
MAD[6] 3-22