Avago Technologies LSI53C1010R - Manual (Page 375)

B-3
Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
Figure B.3 128, 256, 512 Kbyte or 1 Mbyte Interface with 150 ns Memory
LSI53C1010R
27C020-15/
MOE/
OE
MCE/
CE
D[7:0] 8
MAD[7:0]
Bus
CK
Q[7:0]
8
A[7:0]
QE
D[7:0]
CK
Q[7:0]
QE
8
A[15:8]
8
V
DD
MAS0/
MAS1/
8
Note: MAD[2:0] pulled LOW internally. MAD bus sense logic enabled for 128, 256, 512 Kbytes, or 1 Mbyte of fast
memory (150 ns devices @ 66 MHz). The HCT374s may be replaced with HCT377s.
HCT374
HCT374
GPIO4
MWE/
VPP
Control
+12 V
VPP
WE
Optional – for Flash Memory only, not
required for EEPROMs.
28F020-15/
Socket
D[7:0]
MAD3 4.7 K
D[3:0]
CK
Q[3:0]
QE
4
4
HCT377
MAD[3:0]
Bus
E
A[19:16]