Avago Technologies LSI53C1010R - Manual (Page 386)

IX-10 Index
Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
MAD[7:0] 3-18 , 3-22
mailbox one (MBOX1) 2-46 , 4-52
mailbox zero (MBOX0) 2-46 , 4-52
manual start mode (MAN) 4-65
MAS0/ 3-18
MAS1/ 3-18
masking 2-49
master
data parity error (MDPE) 4-41 , 4-66
enable (ME) 4-79
parity error enable (MPEE) 4-57
max SCSI synchronous offset (MO[5:0]) 4-34
maximum stress ratings 6-2
MCE/ 3-18
memory
address strobe 0 3-18
address strobe 1 3-18
address/data bus 3-18
chip enable 3-18
configured as 4-54
I/O address/DSA offset 5-42
move 2-10
move instructions 2-32 , 5-36
no flush option 2-32
move read selector (MMRS) 4-100 , 4-128
move write selector (MMWS) 4-100 , 4-129
output enable 3-18
read 2-13 , 2-14
read caching 2-14
read command 2-6
read line 2-13 , 2-14
read line command 2-8
read multiple 2-13 , 2-14
read multiple command 2-7
space 2-3 , 2-4
to memory 2-18
to memory moves 2-18
write 2-13 , 2-14
write and invalidate 2-13
write and invalidate command 2-9
write caching 2-14
write command 2-6
write enable 3-18
memory interface signals 3-18
MOE/ 3-18
MOE/_TESTOUT 3-18
move to/from SFBR cycles 5-26
multiple cache line transfers 2-10
MWE/ 3-18
N
NC 3-21
new capabilities (NC) 4-6
next item pointer register 4-18
Next_Item_Ptr (NIP[7:0]) 4-18
no flush 5-37
store instruction only 5-41
nonburst opcode fetch
32-bit address and data 6-21
none 2-61
nonfatal interrupts 2-48
normal/fast memory (128 Kbytes)
multiple byte access read cycle 6-48
multiple byte access write cycle 6-50
single byte access read cycle 6-44
single byte access write cycle 6-46
O
objectives of DMA architecture 2-59
opcode 5-10 , 5-16 , 5-25 , 5-29
fetch burst capability 2-32
operating conditions 6-2
operating register/SCRIPTS RAM read
32 bits 6-17
operating register/SCRIPTS RAM write
32 bits 6-19
64 bits 6-20
operator 5-25
output current as a function of output voltage 6-10
output signals 6-5
P
PAR 3-6
PAR64 3-7
parallel
protocol request 2-24
ROM 2-59
ROM support 2-59
parity 3-6
control and generation 2-34
error 3-8 , 4-76
errors and interrupts 2-36
master data parity error 4-41
master parity error enable 4-57
options 2-34
SCSI parity/CRC/AIP error 4-72
parity64 3-7
PCI
address and data signals 3-6
addressing 2-3
arbitration signals 3-8
bus commands and encoding types 2-5
bus commands and functions supported 2-4
cache line size register 2-9
cache mode 2-11