Avago Technologies LSI53C1010R User Manual

Page 144

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Registers

Version 2.2

the arbitration sequence is complete. If a sequence is
aborted, check bit 4 in the SCNTL1 register to verify that
the LSI53C1010R is not connected to the SCSI bus.

WATN

Select with SATN/ on a Start Sequence

When this bit is set and the SCSI function is in the
initiator mode, the SATN/ signal is asserted during
selection of a SCSI target device. This is to inform the
target that the LSI53C1010R SCSI function has a
message to send. If a selection time-out occurs while
attempting to select a target device, SATN/ is deasserted
at the same time SSEL/ is deasserted. When this bit is
cleared, the SATN/ signal is not asserted during
selection. When executing SCSI SCRIPTS, this bit is
controlled by the SCRIPTS processor, but manual setting
is possible in the low level mode.

EPC

Enable Parity/CRC/AIP Checking

When this bit is set and the SCSI transfers are
asynchronous or ST synchronous, the SCSI data bus is
checked for odd parity when data is received from the SCSI
bus in either the initiator or the target mode. If a parity error
is detected, bit 0 of the

SCSI Interrupt Status Zero (SIST0)

When SCSI transfers are DT synchronous, the CRC is
checked when the target requests a CRC transfer using
the DP0 signal on the SCSI bus. If a CRC error is
detected, bit 0 of the

SCSI Interrupt Status Zero (SIST0)

If the LSI53C1010R SCSI function is operating in the
initiator mode and a parity error or CRC error is detected,
SATN/ can optionally be asserted, but the transfer
continues until the target changes phase or the block
move in which the parity error was detected completes.

When this bit is clear, parity errors are not reported. CRC
errors are reported in bit 0 of the

SCSI Interrupt Status Zero (SIST0)

. To disable CRC

checking and reporting, set bit 7, Disable CRC Checking,
of

CRC Control Zero (CRCCNTL0)