Avago Technologies LSI53C1010R - Manual (Page 244)

4-126 Registers
Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
Register: 0x42
Shadowed SCSI SGE Status 0
Read/Write
This register contains the individual status bits that cause an SGE SCSI
interrupt. These bits correspond to the SGE conditions described in the
SIST0 register description. Unlike the other registers in the device, these
bits must be set to one to clear the condition. This register is shadowed
behind the
SCSI Interrupt Status Zero (SIST0) register. It can be
accessed by setting bit 7, the Enable Shadowed SGE Register (ShSGE)
bit, in the
Chip Control Two (CCNTL2) register.
SRP SCRIPTS RAM Parity 7
DFP DMA FIFO Parity 6
RD Residual Data in SCSI FIFO 5
PCO Phase Change with outstanding Offset 4
OO Offset Overflow 3
OU Offset Underflow 2
R Reserved [1:0]
7 6 5 4 3 2 1 0
SRP DFP RD PCO OO OU R
0 0 0 0 0 0 0 0