Avago Technologies LSI53C1010R User Manual

Page 222

4-104

Registers

Version 2.2

the ST edge. Setting this bit reduces the synchronous
send transfer rate but does not reduce the transfer rate at
which the LSI53C1010R can receive inbound REQs, ACKs
or data. Refer to

Table 4.4

and

Table 4.5

for a summary of

available transfer rates and to

Figure 4.1

through

Figure 4.3

for examples of how the XCLKH bits function.

Note:

This bit does not affect CRC timings.

XCLKS_DT

Extra Clock of Data Setup on DT Transfer Edge

Setting this bit adds a clock of data setup to synchronous
DT SCSI transfers on the DT edge. This bit only impacts
DT transfers because it only affects data setup to the DT
edge. Setting this bit reduces the synchronous transfer
send rate but does not reduce the transfer rate at which
the LSI53C1010R can receive inbound REQs, ACKs or
data. Refer to

Table 4.4

and

Table 4.5

for a summary of

available transfer rates and to

Figure 4.1

through

Figure 4.3

for examples of how the XCLKS bits function.

Note:

This bit does not affect CRC timings.

XCLKS_ST

Extra Clock of Data Setup on ST Transfer Edge

Setting this bit adds a clock of data setup to synchronous
DT or ST SCSI transfers on the ST edge. This bit impacts
both ST and DT transfers because it affects data setup to
the ST edge. Setting this bit reduces the synchronous
send transfer rate but does not reduce the transfer rate at
which the LSI53C1010R can receive inbound REQs, ACKs
or data. Refer to

Table 4.4

and

Table 4.5

for a summary of

available transfer rates and to

Figure 4.1

through

Figure 4.3

for examples of how the XCLKS bits function.

Note:

This bit does not affect CRC timings.

Synchronous Receive Rate Calculation
The synchronous receive rate, in megatransfers/s, can be
calculated using the following formula: