Avago Technologies LSI53C1010R - Manual (Page 382)

IX-6 Index
Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
capabilities pointer (CP[7:0]) 4-15
capabilities pointer register 4-15
capability ID (CID[7:0]) 4-18
capability ID register 4-18
carry test 5-33
chained block moves 2-55 , 2-57
chained mode (CHM) 4-31
change bus phases 2-19
chip
control 0 (CCNTL0) 4-93
control 1 (CCNTL1) 4-95
test five (CTEST5) 2-8 , 4-58
test four (CTEST4) 2-35 , 4-57
test one (CTEST1) 4-53
test six (CTEST6) 4-59
test three (CTEST3) 2-9 , 2-13 , 4-55
test two (CTEST2) 4-54
test zero (CTEST0) 4-53
CHMOV 2-55
class code register 4-7
clear DMA FIFO (CLF) 2-51 , 4-56
clear instruction 5-18
clear SCSI FIFO (CSF) 2-51 , 4-90
CLK 3-5
clock 3-5
address incrementor 4-58
byte counter 4-59
conversion factor 4-32
halt SCSI 4-89
quadrupler 2-31
command register 2-13
compare
data 5-34
phase 5-34
configuration
read command 2-6
registers 4-1
space 2-3
write command 2-7
configured
as I/O (CIO) 4-54
as memory (CM) 4-54
connected (CON) 4-29 , 4-49
CRC 1-4 , 2-23
control and generation 2-34
control one (CRCCTNL1) 4-122
control zero (CRCCNTL0) 4-121
data (CRCD) 4-123
data register selector 4-123
disable checking 4-121
disable protocol checking 4-121
enable auto seed 4-122
error 4-122
options 2-34
pad byte value 4-121
pad byte value (CRCPAD) 4-121
request OK 4-27
test CRC accumulate 4-122
test CRC check 4-122
test seed 4-122
CRC-32 1-4
cumulative SCSI byte count (CSBC) 4-120
current
function of input voltage 6-9
function of output voltage 6-10
cycle frame 3-7
cyclic redundancy check 1-4
D
D0 2-62
D1 2-62
D1_Support (D1S) 4-19
D2 2-63
D2_Support (D2S) 4-19
D3 2-63
D3cold 2-63
D3hot 2-63
DACs 2-21
data
(DATA[7:0]) 4-21
compare mask 5-34
compare value 5-35
parity error reported (DPR) 4-6
paths 2-37
register 4-21
structure address (DSA) 4-47
data register 4-21
data_scale (DSCL) 4-20
data_select (DSLT) 4-20
DC characteristics 6-1
default download mode 2-60
destination
address 5-26
I/O-memory enable (DIOM) 4-64
detected parity error (from slave) (DPE) 4-5
device
select 3-8
specific initialization (DSI) 4-19
DEVSEL/ 3-8
timing (DT[1:0]) 4-5
DIEN 2-48
differential mode 2-39
DIP 2-51
direct 5-21