Avago Technologies LSI53C1010R - Manual (Page 98)

3-4 Signal Descriptions
Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
3.2 Internal Pull-ups and Pull-downs on LSI53C1010R Signals
Several LSI53C1010R signals use internal pull-ups and pull-downs.
Table 3.1 describes the conditions that enable these pull-ups and
pull-downs.
Table 3.1 LSI53C1010R Internal Pull-ups and Pull-downs
Pin Name
Pull-up
Current (
µ
A) Conditions for Pull-up
INTA/, INTB/, ALT_INTA/,
ALT_INTB/ 25 Pull-up enabled when the “AND-tree” mode is enabled by
driving TEST_RST/ LOW or when the IRQ mode bit
(bit 3 of DCNTL, 0X3B) is cleared.
1
ENABLE66, M66EN,
TCK_CHIP, TDI_CHIP,
TEST_RST/, TMS_CHIP 25 Pulled up internally.
AD[63:32], C_BE[7:4]/,
PAR64 25 Pulled down internally.
GPIO[4:0] 25 Pulled down internally.
MAD[7:0] 25 Pulled down internally.
SCAN_MODE,
TEST_HSC 25 Pulled down internally.
SCANEN, IDDTN 25 Pulled down internally.
1. When bit 3 of the DMA Control (DCNTL) register is set, the pad becomes a totem pole output pad
and drives both HIGH and LOW.