Avago Technologies LSI53C1010R - Manual (Page 267)

I/O Instructions 5-19
Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
before the selection completes. It continues executing
SCRIPTS until a SCRIPT that requires a response from
the target is encountered.
If the LSI53C1010R is selected or reselected before
winning arbitration, it fetches the next instruction from the
address pointed to by the 32-bit jump address field stored
in the
DMA Next Address (DNAD) register. Manually set
the LSI53C1010R to the initiator mode if it is reselected,
or to the target mode if it is selected.
If the Select with SATN/ field is set, the SATN/ signal is
asserted during the selection phase.
Wait Disconnect Instruction
The LSI53C1010R waits for the target to perform a “legal”
disconnect from the SCSI bus. A “legal” disconnect
occurs when SBSY/ and SSEL/ are inactive for a
minimum of one Bus Free delay (400 ns), after the
LSI53C1010R receives a Disconnect Message or a
Command Complete Message.
Wait Reselect Instruction
If the LSI53C1010R is selected before being reselected,
it fetches the next instruction from the address pointed to
by the 32-bit jump address field stored in the
DMA Next Address (DNAD) register. Manually set the
LSI53C1010R to the target mode when it is selected.
If the LSI53C1010R is reselected, it fetches the next
instruction from the address pointed to by the
DMA SCRIPTS Pointer (DSP) register.
If the CPU sets the SIGP bit in the
Interrupt Status Zero (ISTAT0) register, the LSI53C1010R
aborts the Wait Reselect instruction and fetches the next
instruction from the address pointed to by the 32-bit jump
address field stored in the
DMA Next Address (DNAD)
register.
Set Instruction
When the SACK/ or SATN/ bits are set, the corresponding
bits in the
SCSI Output Control Latch (SOCL) register are
set. When the target bit is set, the corresponding bit in the
SCSI Control Zero (SCNTL0) register is also set. When
the carry bit is set, the corresponding bit in the ALU is set.