Avago Technologies LSI53C1010R User Manual
Page 261
Block Move Instructions
5-13
Version 2.2
Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
If the SCSI phase bits match the value stored in the
register, the LSI53C1010R
transfers the number of bytes specified in the
register starting at the address
pointed to by the
register. If the
opcode bit is cleared and a data transfer ends on an odd
byte boundary, the LSI53C1010R stores the last byte in the
register during a receive
operation, or in the
register during a send operation. This byte is combined
with the first byte from the subsequent transfer so that a
wide transfer can complete.
If the SCSI phase bits do not match the value stored in
the
register, the
LSI53C1010R generates a phase mismatch interrupt and
the instruction is not executed.
During a Message-Out phase, after the LSI53C1010R
has performed a select with Attention (or SATN/ is
manually asserted with a Set ATN instruction), the
LSI53C1010R deasserts SATN/ during the final
SREQ/SACK/ handshake.
When the LSI53C1010R is performing a block move for
Message-In phase, it does not deassert the SACK/ signal
for the last SREQ/SACK/ handshake. Clear the SACK/
signal using the Clear SACK I/O instruction.
SCSIP[2:0]
SCSI Phase
[26:24]
This field defines the desired SCSI information transfer
phase. When the LSI53C1010R operates in the initiator
mode, these bits are compared with the latched SCSI
phase bits in the
register.
When the LSI53C1010R operates in the target mode, it
asserts the phase defined in this field. The following table
describes the possible combinations and the
corresponding SCSI phase.