10 parity/crc/aip options, Parity/crc/aip options – Avago Technologies LSI53C1010R User Manual
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Functional Description
Version 2.2
Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
2.2.10 Parity/CRC/AIP Options
The LSI53C1010R implements a flexible parity scheme that permits
control of the parity sense, allows parity checking to be turned on or off,
and can deliberately send a byte with bad parity over the SCSI bus.
defines the bits that are involved in parity control and
observation.
describes the parity control function of the
Enable Parity Checking and Assert SCSI Even Parity bits in the
register, bit 2, and the options available
when a parity error occurs.
SCRIPTS RAM must first be written before being read in order to
initialize SCRIPTS RAM parity. If a SCRIPTS RAM parity error is
encountered, a SCSI Gross Error interrupt is signaled.
The LSI53C1010R supports CRC checking and generation in DT phases
and CRC checking and generation during DT Data Transfers.
The new CRC registers are:
;
;
, bit 3, EPC, and bit 1,
AAP;
, bit 5, DHP; and
SCSI Interrupt Enable Zero (SIEN0)
, bit 0 (SCSI Parity/CRC/AIP Error).
The new AIP registers are:
,
, and
.
Table 2.4
Bits Used for Parity/CRC/AIP Control and Generation
Bit Name
Location
Description
AAP (Assert SATN/ on
Parity/CRC/AIP Errors)
, Bit 1
When this bit is set, the LSI53C1010R SCSI function
automatically asserts the SATN/ signal upon detection
of a parity, CRC, or AIP error. SATN/ is only asserted in
initiator mode.
EPC (Enable
Parity/CRC/AIP
Checking)
, Bit 3
When set, this bit enables parity checking on the
LSI53C1010R. The LSI53C1010R checks for odd parity.
Assert Even SCSI
Parity
, Bit 2
When set, this bit forces even SCSI parity on each byte
sent to the SCSI bus from the LSI53C1010R.
Disable Halt on SATN/
or Parity/CRC/AIP Error
(Target Mode Only)
, Bit 5
This bit determines whether the LSI53C1010R halts
operations when a parity error is detected in target mode.