Avago Technologies LSI53C1010R - Manual (Page 365)

LSI53C1010R PCI to Dual Channel Ultra160 SCSI Multifunction Controller A-1
Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
Appendix A
Register Summary
Table A.1 lists the LSI53C1010R PCI registers by register name.
Table A.1 LSI53C1010R PCI Register Map
Register Name Address Read/Write Page
PCI Registers
Base Address Register Four (BAR4) (SCRIPTS RAM) 0x20–0x23 Read/Write 4-11
Base Address Register One (BAR1) (MEMORY) 0x14–0x17 Read/Write 4-9
Base Address Register Three (BAR3) (SCRIPTS RAM) 0x1C–0x1F Read/Write 4-10
Base Address Register Two (BAR2) (MEMORY) 0x18–0x1B Read/Write 4-10
Base Address Register Zero (BAR0) (I/O) 0x10–0x13 Read/Write 4-9
Bridge Support Extensions (PMCSR_BSE) 0x46 Read Only 4-21
Cache Line Size (CLS) 0x0C Read/Write 4-7
Capabilities Pointer (CP) 0x34 Read Only 4-15
Capability ID (CID) 0x40 Read Only 4-18
Class Code (CC) 0x09–0x0B Read Only 4-7
Command 0x04–0x05 Read/Write 4-3
Data 0x47 Read Only 4-21
Device ID 0x02–0x03 Read Only 4-3
Expansion ROM Base Address (ERBA) 0x30–0x33 Read/Write 4-14
Header Type (HT) 0x0E Read Only 4-8
Interrupt Line (IL) 0x3C Read/Write 4-16
Interrupt Pin (IP) 0x3D Read Only 4-16