Avago Technologies LSI53C1010R - Manual (Page 13)

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Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
6.40 Initiator and Target DT Synchronous Transfer 6-65
6.41 LSI53C1010R 456 BGA Chip – Top View 6-68
6.42 LSI53C1010R 456 BGA Mechanical Drawing 6-74
B.1 16 Kbyte Interface with 200 ns Memory B-1
B.2 64 Kbyte Interface with 150 ns Memory B-2
B.3 128, 256, 512 Kbyte or 1 Mbyte Interface
with 150 ns Memory
B-3
B.4 512 Kbyte Interface with 150 ns Memory B-4