Avago Technologies LSI53C1010R User Manual
Page 37
PCI Functional Description
2-7
Version 2.2
Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
2.1.2.9 Configuration Write Command
The Configuration Write command writes the configuration space of a
device. The LSI53C1010R never generates this command as a master,
but does respond to it as a slave. A device on the PCI bus selects the
LSI53C1010R by asserting its IDSEL signal when AD[1:0] are 0b00.
During the address phase of a configuration cycle, AD[7:2] address one
of the 64 Dword registers in the configuration space of each device.
C_BE[3:0]/ address the individual bytes within each Dword. AD[10:8]
indicate which device on the LSI53C1010R is being addressed. The
LSI53C1010R treats AD[63:11] as logical don’t cares.
2.1.2.10 Memory Read Multiple Command
This command is identical to the Memory Read command, except it
additionally indicates that the master intends to fetch multiple cache lines
before disconnecting. The LSI53C1010R supports PCI Memory Read
Multiple functionality and issues Memory Read Multiple commands on the
PCI bus when the Read Multiple mode is enabled. This mode is enabled
by setting bit 2 (ERMP) of the
register. If the cache
mode is enabled, a Memory Read Multiple command is issued on all read
cycles, except opcode fetches, when the following conditions are met:
•
The CLSE bit (Cache Line Size Enable, bit 7,
register) is set.
•
The ERMP bit (Enable Read Multiple, bit 2,
register) is set.
•
The
register for each function contains a
legal burst size value (8, 16, 32, 64, or 128 Dwords) that is less than
or equal to the DMODE burst size.
•
The transfer crosses a cache line boundary.
When these conditions are met, the chip issues a Memory Read Multiple
command instead of a Memory Read during all PCI read cycles.
Burst Size Selection – The Read Multiple command reads in multiple
cache lines of data during a single bus ownership. Revision 2.2 of the PCI
specification specifies the number of cache lines to read as a multiple of
the cache line size. The logic selects the largest multiple of the cache line