Dma interrupt enable (dien), Register: 0x39 – Avago Technologies LSI53C1010R User Manual
Page 184
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Registers
Version 2.2
Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
Register: 0x39
DMA Interrupt Enable (DIEN)
Read/Write
This register contains the interrupt mask bits corresponding to the
interrupting conditions described in the
register. An
interrupt is masked by clearing the appropriate mask bit. Masking an
interrupt prevents INTA/ (for Function A) or INTB/ (for Function B) from
being asserted for the corresponding interrupt, but the status bit is still
set in the
register. Masking an interrupt does not
prevent setting the
Interrupt Status Zero (ISTAT0)
DIP. All DMA interrupts
are considered fatal. Therefore, SCRIPTS halts when this condition
occurs, whether or not the interrupt is masked. Setting a mask bit
enables the assertion of INTA/, or INTB/, for the corresponding interrupt.
A masked nonfatal interrupt does not prevent unmasked or fatal
interrupts from getting through; interrupt stacking begins when either the
Interrupt Status Zero (ISTAT0)
SIP or DIP bit is set.
The INTA/ and INTB/ outputs are latched. When asserted, they remain
asserted until the interrupt is cleared by reading the appropriate status
register. Masking an interrupt after the INTA/, or INTB/, output is asserted
does not cause deassertion of INTA/ or INTB/. For details on interrupts,
refer to
Chapter 2, “Functional Description.”
R
Reserved
7
MDPE
Master Data Parity Error
6
BF
Bus Fault
5
ABRT
Aborted
4
SSI
Single Step Interrupt
3
SIR
SCRIPTS Interrupt Instruction Received
2
R
Reserved
1
IID
Illegal Instruction Detected
0
7
6
5
4
3
2
1
0
R
MDPE
BF
ABRT
SSI
SIR
R
IID
x
0
0
0
0
0
x
0