Avago Technologies LSI53C1010R - Manual (Page 206)

4-88 Registers
Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
Register: 0x4E
SCSI Test Two (STEST2)
Read/Write
SCE SCSI Control Enable 7
Setting this bit allows assertion of all SCSI control and
data lines through the
SCSI Output Control Latch (SOCL)
and SCSI Output Data Latch (SODL) registers regardless
of whether the LSI53C1010R SCSI function is configured
as a target or initiator.
Note: Do not set this bit during normal operation, because it could
cause contention on the SCSI bus. It is included for
diagnostic purposes only.
ROF Reset SCSI Offset 6
Setting this bit clears any outstanding synchronous
SREQ/SACK offset. If a SCSI gross error occurs, set this
bit. This bit automatically clears itself after resetting the
synchronous offset.
R Reserved [5:4]
SZM SCSI High Impedance Mode 3
Setting this bit places all the open-drain 48 mA SCSI
drivers into a high impedance state.
R Reserved [2:1]
LOW SCSI Low Level Mode 0
Setting this bit places the LSI53C1010R SCSI function in
the low level mode. In this mode, no DMA operations
occur and no SCRIPTS execute. Arbitration and selection
may be performed by setting the start sequence bit as
described in the
SCSI Control Zero (SCNTL0) register.
SCSI bus transfers are performed by manually asserting
and polling SCSI signals. Clearing this bit allows
instructions to be executed in the SCSI SCRIPTS mode.
7 6 5 4 3 2 1 0
SCE ROF R SZM R LOW
0 0 0 0 0 0 0 0