Avago Technologies LSI53C1010R - Manual (Page 213)

SCSI Registers 4-95
Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
Register: 0x57
Chip Control One (CCNTL1)
Read/Write
PULLDIS Pull Disable 7
Setting this bit causes all internal pulls to be disabled on
all pins. This bit is intended for manufacturing test only
and should not be set for normal operation. PULLDIS has
precedence over PULLEN if both bits are set.
PULLEN Pull Enable 6
Setting this bit causes all internal pulls to be enabled on
all pins. This bit is intended for manufacturing test only
and should not be set for normal operation.
DIS64MAS Disable 64-bit Master Operation 5
Setting this bit causes the LSI53C1010R to no longer
request 64-bit master data transfers. If this bit is set by
either SCSI channel, 64-bit data transfers are disabled for
all master transactions.
DIS64SLV Disable 64-bit Slave Cycles 4
Setting this bit disables 64-bit slave data transfers to the
SCRIPT RAM. This causes only 32-bit transfers to occur.
DDAC Disable Dual Address Cycle 3
When this bit is set, all 64-bit addressing as a master is
disabled. No dual address cycles are generated by the
LSI53C1010R.
When this bit is cleared, the LSI53C1010R generates dual
address cycles based on the master operation performed
and the value of its associated selector register.
64TIMOD 64-Bit Table Indirect Indexing Mode 2
When this bit is cleared, bits [28:24] of the first table entry
Dword select one of 22 possible selectors to be used in
a BMOV operation. When this bit is set, bits [31:24] of the
first table entry Dword are copied directly into
7 6 5 4 3 2 1 0
PULLDIS PULLEN DIS64MAS DIS64SLV DDAC 64TIMOD EN64TIBMV EN64DBMV
0 0 0 0 x x 0 0