Avago Technologies LSI53C1010R - Manual (Page 347)

PCI and External Memory Interface Timing Diagrams 6-57
Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
Figure 6.34
≤
64 Kbytes ROM Write Cycle
Table 6.38
≤
64 Kbytes ROM Write Cycle
Symbol Parameter Min Max Unit
t
11
Address setup to MAS/ HIGH 25 – ns
t
12
Address hold from MAS/ HIGH 15 – ns
t
13
MAS/ pulse width 25 – ns
t
20
Data setup to MWE/ LOW 30 – ns
t
21
Data hold from MWE/ HIGH 20 – ns
t
22
MWE/ pulse width 100 – ns
t
23
Address setup to MWE/ LOW 60 – ns
t
24
MCE/ LOW to MWE/ HIGH 120 – ns
t
25
MCE/ LOW to MWE/ LOW 25 – ns
t
26
MWE/ HIGH to MCE/ HIGH 25 – ns
CLK
(Driven by System)
1 2 3 4 5 6 7 8 9 10
MAD
(Driven by LSI53C1010R)
High Order
Address
Low Order
Address
MAS1/
(Driven by LSI53C1010R)
MAS0/
(Driven by LSI53C1010R)
MCE/
(Driven by LSI53C1010R)
MOE/
(Driven by LSI53C1010R)
MWE/
(Driven by LSI53C1010R)
t
13
t
11
t
12
t
22
11 12 13
t
24
t
21
Valid Write Data
t
23
t
25
t
26
t
20