Avago Technologies LSI53C1010R - Manual (Page 137)

PCI Configuration Registers 4-19
Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
Registers: 0x42–0x43
Power Management Capabilities (PMC)
Read Only
PMES PME_Support [15:11]
Bits [15:11] define the power management states in
which the LSI53C1010R asserts the PME pin. These bits
are all set to zero because the LSI53C1010R does not
provide a PME signal.
D2S D2_Support 10
The LSI53C1010R sets this bit to indicate support for
power management state D2. Bits 9 and 10 are set to
indicate support for the D1 and D2 power states.
D1S D1_Support 9
The LSI53C1010R sets this bit to indicate support for
power management state D1. Bits 9 and 10 are set to
indicate support for the D1 and D2 power states.
AUX_C Aux_Current [8:6]
The LSI53C1010R always returns zeros. This feature is
not supported.
DSI Device Specific Initialization 5
This bit is cleared to indicate that the LSI53C1010R
requires no special initialization before the generic class
device driver is able to use it.
R Reserved 4
PMEC PME Clock 3
Bit 3 is cleared because the LSI53C1010R does not
provide a PME pin.
VER[2:0] Version [2:0]
These three bits are set to 0b010 to indicate that the
LSI53C1010R complies with Revision 1.1 of the PCI
Power Management Interface Specification.
15 11 10 9 8 6 5 4 3 2 0
PMES D2S D1S AUX_C DSI R PMEC VER[2:0]
0 0 0 0 0 1 1 0 0 0 0 0 0 0 1 0