Avago Technologies LSI53C1010R - Manual (Page 367)

A-3
Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
Table A.2 lists the LSI53C1010R SCSI registers, Phase Mismatch Jump
registers, and Shadow registers by register name.
Table A.2 LSI53C1010R SCSI Register Map
Register Name Address Read/Write Page
SCSI Registers
Adder Sum Output (ADDER) 0x3C–0x3F Read Only 4-70
AIP Control One (AIPCNTL1) 0xBF Read/Write 4-114
AIP Control Zero (AIPCNTL0) 0xBE Read Only 4-113
Chip Control One (CCNTL1) 0x57 Read/Write 4-95
Chip Control Three (CCNTL3) 0x5B Read/Write 4-98
Chip Control Two (CCNTL2) 0x5A Read/Write 4-97
Chip Control Zero (CCNTL0) 0x56 Read/Write 4-93
Chip Test Five (CTEST5) 0x22 Read/Write 4-58
Chip Test Four (CTEST4) 0x21 Read/Write 4-57
Chip Test One (CTEST1) 0x19 Read Only 4-53
Chip Test Six (CTEST6) 0x23 Read/Write 4-59
Chip Test Three (CTEST3) 0x1B Read/Write 4-55
Chip Test Two (CTEST2) 0x1A Read Only
(bit 3 write) 4-54
Chip Test Zero (CTEST0) 0x18 Read/Write 4-53
Current Inbound SCSI Offset (CSO) 0x53 Read Only 4-92
Data Structure Address (DSA) 0x10–0x13 Read/Write 4-47
DMA Byte Counter (DBC) 0x24–0x26 Read/Write 4-60
DMA Command (DCMD) 0x27 Read/Write 4-61
DMA Control (DCNTL) 0x3B Read/Write 4-67
DMA Interrupt Enable (DIEN) 0x39 Read/Write 4-66
DMA Mode (DMODE) 0x38 Read/Write 4-63
DMA Next Address (DNAD) 0x28–0x2B Read/Write 4-61