Avago Technologies LSI53C1010R User Manual
Page 86
2-56
Functional Description
Version 2.2
Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
2.2.18.1 Wide SCSI Send Bit
The WSS bit is set following a wide SCSI send operation (Data-Out for
initiator mode or Data-In for target mode) when the SCSI core is holding
a byte of chain data. The SCSI core holds the byte when the controller
detects a partial transfer at the end of a Chained Block Move SCRIPTS
instruction. This flag is not set if a normal Block Move instruction is used.
Under this condition, the SCSI controller does not send the low-order
byte of the last partial memory transfer across the SCSI bus. Instead, the
low-order byte is temporarily stored in the lower byte of the
register for asynchronous transfers or
in the chain byte holding register for synchronous transfers, and the WSS
flag is set.
The hardware uses the WSS bit to determine what behavior must occur
at the start of the next data send transfer. If the WSS bit is set at the
start of the next transfer, the first byte (the high-order byte) of the next
data send transfer is “married” with the byte of chain data. The two bytes
are sent out across the bus regardless of the type of Block Move
instruction (normal or chained). The WSS bit is automatically cleared
when the “married” word is sent. Performing either a SCSI receive
operation or any narrow transfer also clears the bit. In addition, SCRIPTS
and the microprocessor can clear the WSS bit as well as use it for error
detection and recovery purposes.
2.2.18.2 Wide SCSI Receive Bit
The WSR bit is set following a wide SCSI receive operation (Data-In for
initiator mode or Data-Out for target mode) when the SCSI core is
holding a byte of chain data. The SCSI core holds the byte when the
controller detects a partial transfer at the end of a Chained Block Move
instruction. Under this condition the high-order byte is not transferred out
the DMA channel to memory. Instead, it is stored in the
register and the WSR flag is set.
The hardware uses the WSR bit to determine what behavior must occur at
the start of the next data receive transfer. If set, the stored high-order byte
may be residual data, valid data for a subsequent data transfer, or overrun
data. The byte may be read as normal by starting a data receive transfer.
The WSR bit is automatically cleared at the start of the next data receive