Avago Technologies LSI53C1010R - Manual (Page 15)

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Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
Tables
2.1 PCI Bus Commands and Encoding Types 2-5
2.2 PCI Cache Mode Alignment 2-12
2.3 New Phases on SCSI Bus 2-24
2.4 Bits Used for Parity/CRC/AIP Control and Generation 2-34
2.5 SCSI Parity Errors and Interrupts 2-36
2.6 SCF Divisor Values 2-42
2.7 Parallel ROM Support 2-59
2.8 Default Download Mode Serial EEPROM Data Format 2-61
2.9 Power States 2-62
3.1 LSI53C1010R Internal Pull-ups and Pull-downs 3-4
3.2 System Signals 3-5
3.3 Address and Data Signals 3-6
3.4 Interface Control Signals 3-7
3.5 Arbitration Signals 3-8
3.6 Error Reporting Signals 3-8
3.7 Interrupt Signals 3-9
3.8 SCSI Bus Interface Signal 3-10
3.9 SCSI Function A Signals 3-10
3.10 SCSI Function A Control Signals 3-12
3.11 SCSI Function B Signals 3-13
3.12 SCSI Function B Control Signals 3-15
3.13 SCSI Function A GPIO Signals 3-16
3.14 SCSI Function B GPIO Signals 3-17
3.15 Flash ROM and Memory Interface Signals 3-18
3.16 Test Interface Signals 3-19
3.17 Power and Ground Signals 3-20
3.18 MAD[3:1] Pin Decoding 3-23
4.1 PCI Configuration Register Map 4-2
4.2 SCSI Register Map 4-23
4.3 Maximum Synchronous Offset 4-35
4.4 Double Transition Transfer Rates 4-109
4.5 Single Transition Transfer Rates 4-111
5.1 Read/Write Instructions 5-27
6.1 Absolute Maximum Stress Ratings 6-2
6.2 Operating Conditions 6-2