Avago Technologies LSI53C1010R - Manual (Page 392)

IX-16 Index
Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
T
table indirect 5-7 , 5-21
64-bit indexing mode 4-95
index mode mapping 5-10
mode 5-20
table relative 5-22
target
asynchronous receive 6-60
asynchronous send 6-59
mode 5-10 , 5-16
SATN/ active (M/A) 4-74
mode (TRG) 4-27
ready 3-7
synchronous transfer 6-62 , 6-65
timing 6-14
TCK_CHIP 3-19
TDI_CHIP 3-19
TDO_CHIP 3-19
TEMP register 5-39
temporary register (TEMP) 4-56
termination 2-39
test
clock 3-19
CRC accumulate 4-122
CRC check 4-122
CRC seed 4-122
data in 3-19
data out 3-19
halt SCSI clock 3-19
interface signals 3-19
mode select 3-19
reset 3-19
TEST_HSC 3-4 , 3-19
TEST_RST/ 3-19
third dword 5-15 , 5-35 , 5-38
time-out 4-77
timer test mode (TTM) 4-90
timing diagrams 6-13
TMS_CHIP 3-19
TolerANT 1-6
enable (TE) 4-89
technology 1-6
benefits 1-6
totem pole output 3-2
transfer
control 2-32
control instructions 5-28
and SCRIPTS instruction prefetching 2-32
count 5-37
counter 5-14
information 2-19
period factor 2-25
rate synchronous 2-41
width exponent 2-25
TRDY/ 2-10 , 3-7
U
Ultra SCSI
single-ended transfers 6-61 , 6-63
Ultra160 SCSI 1-4
benefits 1-4
designing an Ultra160 SCSI system 2-22
enabling 2-27
transfer enable 4-103
transfers 6-65
Ultra2 SCSI
transfers 6-62 , 6-64
unexpected disconnect (UDC) 4-72 , 4-76
updated address (UA) 4-117
upper register address line (A7) 5-25
use data8/SFBR 5-25
V
VDD_IO 3-20
VDDA 3-20
VDDBIAS 3-21
VDDC 3-20
vendor
ID register 4-2
unique enhancement, bit 1 (VUE1) 4-31
unique enhancements, bit 0 (VUE0) 4-31
VER[2:0]) 4-19
version (VER[2:0]) 4-19
VID 4-2
VSS_IO 3-20
VSSA 3-21
VSSC 3-20
W
wait
disconnect instruction 5-19
for disconnect 2-19
for valid phase 5-34
reselect instruction 5-19
select instruction 5-17
wide SCSI
chained block moves 2-55
receive (WSR) 4-31
receive bit 2-56
send (WSS) 4-31
send bit 2-56
won arbitration (WOA) 4-45