Digi NS9750 - Manual (Page 893)

I - I n d e x - 2 3
R0, ID code and cache type status
registers
55
-
57
R1, Control register 58 - 60
R10, TLB Lockdown register 73
R11 register 74
R12 register 74
R13, Process ID register
75
-
77
R14 register 77
R15, Test and debug register 77
R2, Translation Table Base register 61
R3, Domain Access Control
register
61
,
98
R4 register
62
R5, Fault Status registers 62
R6, Fault Address register 64 , 97
R7, Cache Operations register 64 - 68
R8, TLB Operations register 68
R9, Cache Lockdown register
69
-
73
summary 53
System Memory Chip Select 0 Dynamic
Memory Base and Mask
registers
303
System Memory Chip Select 0 Static
Memory Base and Mask
registers
307
System Memory Chip Select 1 Dynamic
Memory Base and Mask
registers
304
System Memory Chip Select 1 Static
Memory Base and Mask
registers
308
System Memory Chip Select 2 Dynamic
Memory Base and Mask
registers
305
System Memory Chip Select 2 Static
Memory Base and Mask
registers
309
System Memory Chip Select 3 Dynamic
Memory Base and Mask
registers
306
System Memory Chip Select 3 Static
Memory Base and Mask
registers
310
system memory interface
pinout 18
signals
22
system timers
6
system-level interfaces 8
T
TFT display panels 564
TFT displays 565
Timer 0-15 Control registers
301
Timer 0-15 Read register
285
Timer 0-15 Reload Count registers 284
Timer Interrupt Status register 291
timing 787 - 839
about 787
absolute maximum ratings
788
clock timing
837
-
839
DC electrical characteristics 790 - 791
inputs 790
outputs 791
electrical characteristics 788 - 789
Ethernet timing
813
-
815
I2C timing 821
IEEE 1284 timing 831
JTAG timing 836
LCD timing 822 - 826
maximum power dissipation
789
memory timing
795
-
812
PCI timing 816 - 820
recommended operating
conditions 788
reset and hardware strapping
835
SPI timing
827
-
830
USB timing 832 - 834