Digi NS9750 User Manual
Page 236
R e g i s t e r s
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N S 9 7 5 0 H a r d w a r e R e f e r e n c e
Dynamic Memory Read Configuration register
Address: A070 0028
The Dynamic Memory Read Configuration register allows you to configure the dynamic
memory read strategy. Modify this register only during system initialization.
Note:
The Dynamic Memory Read Configuration register is used for all four
dynamic memory chip selects. The worst case value for all chip selects
must be programmed.
Register bit assignment
Bits
Access
Mnemonic
Description
D31:02
N/A
Reserved
N/A (do not modify)
D01:00
RW
RD
Read data strategy
00
Reserved.
01
Command delayed strategy, using
CLKDELAY
(command
delayed, clock out not delayed).
10
Command delayed strategy plus one clock cycle, using
CLKDELAY
(command delayed, clock out not delayed).
11
Command delayed strategy plus two clock cycles, using
CLKDELAY
(command delayed, clock out not delayed).
Table 143: Dynamic Memory Read Configuration register
13
12
11
10
9
8
7
6
5
4
3
2
1
0
15
14
31
29
28
27
26
25
24
23
22
21
20
19
18
17
16
30
Reserved
Reserved
RD