Digi NS9750 - Manual (Page 880)

I n d e x - 10
I
I bit, Ethernet 326 , 328
I2C
bus arbitration 547
command interface
545
Command Transmit Data register 548
Configuration register 552
external addresses 545
locked interrupt driven mode 546
Master Address register 550
master module commands
546
master module flowchart 556
master software driver 555
master/slave interface 543 - 557
module 544
physical bus
544
register addresses
547
Slave Address register 551
slave module commands 546
slave module flowchart 557
Status Receive Data register 549
timing diagram
821
I2C controller
port features 5
I2C pinout 43
I2C timing 821
ICache, instruction cache 51 , 56 , 105 , 107
IDLE condition
605
IEEE 1284
BBus slave and DMA interface
module 677 - 705
Buffer Full Status register 703
byte mode
672
compatibility mode 671
Core Phase (IEEE 1284) register 704
data and command FIFOs 675
ECP mode 673 - 674
Extended Control register 698
Extensibility Byte Requested by Host
register 698
extensibility byte values 676
Feature Control Register A 694
Feature Control Register B 695
FIFO Status register
684
Forward Address register 703
Forward Command DMA Control
register 689
Forward Command FIFO Read
register
686
Forward Data DMA Control
register 690
Forward Data FIFO Read register 687
General Configuration register 679
Granularity Count register
702
Interrupt Enable register 695
Interrupt Status and Control
register 681
Interrupt Status register 699
Interrupt Timeout Counter
register 700
Master Enable register 697
negotiation 676
nibble mode 672
peripheral controller
669
-
705
peripheral port control module 670
Pin Interrupt Control register 701
Pin Interrupt Mask register 700
Port Control register 693
Port Status register, host
692
Port Status register, peripheral
694
Printer Data Pins register 691
register map (BBus slave and DMA
interface) 677
requirements
670
Reverse FIFO Write register
687
Reverse FIFO Write Register - Last 687