Digi NS9750 User Manual
Page 84

S y s t e m c o n t r o l p r o c e s s o r ( C P 1 5 ) r e g i s t e r s
6 0
N S 9 7 5 0 H a r d w a r e R e f e r e n c e
The M, C, I, and RR bits directly affect ICache and DCache behavior, as shown:
If either the DCache or ICache is disabled, the contents of that cache are not
accessed. If the cache subsequently is re-enabled, the contents will not have
changed. To guarantee that memory coherency is maintained, the DCache must be
cleaned of dirty data before it is disabled.
[0]
M bit
MMU enable/disable
0
Disabled
1
Enabled
Cache
MMU
Behavior
ICache disabled
Enabled or disabled
All instruction fetches are from external memory (AHB).
ICache enabled
Disabled
All instruction fetches are cachable, with no protection
checking. All addresses are flat-mapped; that is:
VA=MVA=PA.
ICache enabled
Enabled
Instruction fetches are cachable or noncachable, and
protection checks are performed. All addresses are
remapped from VA to PA, depending on the MMU page
table entry; that is, VA translated to MVA, MVA
remapped to PA.
DCache disabled
Enabled or disabled
All data accesses are to external memory (AHB).
DCache enabled
Disabled
All data accesses are noncachable nonbufferable. All
addresses are flat-mapped; that is, VA=MVA=PA.
DCache enabled
Enabled
All data accesses are cachable or noncachable, and
protection checks are performed. All addresses are
remapped from VA to PA, depending on the MMU page
table entry; that is, VA translated to MVA, MVA
remapped to PA.
Table 23: Effects of Control register on caches
Bits
Name
Function
Table 22: R1: Control register bit definition