Pci bus arbiter – Digi NS9750 User Manual

Page 442

P C I b u s a r b i t e r

4 1 8

N S 9 7 5 0 H a r d w a r e R e f e r e n c e

PCI Subsystem ID register

Read-only value. To change this value, use the

SUBSYSTEM_ID

field in the PCI

Configuration 2 register (see page 430) in the PCI arbiter.

PCI Expansion ROM register

Read-only value, hardwired to

0x00000000

PCI Interrupt Line register

Read/write value indicating to which line of an interrupt controller the PCI interrupt
generated by the bridge is connected. This register is used only in those systems in
which NS9750 is not handling PCI interrupts.

PCI Interrupt Pin register

Read-only value programmed using the

INTERRUPT_PIN

field in the PCI Configuration 3

0x1

(default value) when

NS9750 drives

INTA#

PCI Min Grant register

Read-only value programmed using the

MIN_GRANT

field in the PCI Configuration 3

PCI Max Latency register

Read-only value programmed using the

MAX_LATENCY

field in the PCI Configuration 3

PCI bus arbiter

NS9750 provides an embedded PCI bus arbiter that supports up to three external PCI
masters and the internal PCI-to-AHB bridge. The arbiter uses a rotating priority
scheme. An AHB slave is integrated with the PCI bus arbiter to access programmable
registers, to support system configuration and error reporting.