Pci bridge interrupt enable register – Digi NS9750 User Manual
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P C I - t o - A H B B r i d g e
Register bit assignment
PCI Bridge Interrupt Enable register
Address: A030 0030
The PCI Bridge Interrupt Enable register stores the enables for all interrupt sources.
Register bit assignment
Bits
Access
Mnemonic
Reset
Description
D31:01
Hardwired to
0
Reserved
N/A
N/A
D00
R/C
AHBERR
0
AHB bus error
Table 271: PCI Bridge Interrupt Status register
Bits
Access
Mnemonic
Reset
Description
D31:16
Hardwired to
0
Reserved
N/A
N/A
D15
R/W
PDPERREN
0
PCI detected parity error enable
0
Interrupt disabled
1
Interrupt enabled
Bit 15 of PCI Status register
D14
R/W
PSYSEREN
0
PCI signaled system error enable
0
Interrupt disabled
1
Interrupt enabled
Bit 14 of PCI Status register
Table 272: PCI Bridge Interrupt Enable register
Reserved
AHB
ERR
EN
13
12
11
10
9
8
7
6
5
4
3
2
1
0
15
14
31
29
28
27
26
25
24
23
22
21
20
19
18
17
16
30
Reserved
Reserved
PDP
ERR
EN
PSYS
EREN
PRX
MAEN
PRXT
ARN
PSIG
TAEN
PMP
ERR
EN