Phy support register, Register bit assignment – Digi NS9750 User Manual
Page 382
E t h e r n e t C o n t r o l a n d S t a t u s r e g i s t e r s
3 5 8
N S 9 7 5 0 H a r d w a r e R e f e r e n c e
PHY Support register
Address: A060 0418
Register bit assignment
Bits
Access
Mnemonic
Reset
Description
D31:16
N/A
Reserved
N/A
N/A
D15
R/W
RPERMII
0
Reset RMII module
Set to 1 to reset the RMII PHY interface module logic.
D14:09
R/W
Not used
0x08
Always write 0x08.
D08
R/W
SPEED
0
Speed select (RMII)
0
RMII PHY interface logic is configured for 10
Mbps
1
RMII PHY interface logic is configured for 100
Mbps
D07:00
R?W
Not used
0x00
Always write 0x00.
Table 217: PHY Support register
Reserved
13
12
11
10
9
8
7
6
5
4
3
2
1
0
15
14
31
29
28
27
26
25
24
23
22
21
20
19
18
17
16
30
RPER
MII
Not used
SPEED
Not used