Digi NS9750 - Manual (Page 81)

w w w . d i g i e m b e d d e d . c o m 5 7
W o r k i n g w i t h t h e C P U
Dsize and Isize fields
The Dsize and Isize fields in the cache type register have the same format, as shown:
The field contains these bits:
Field Description
Size Determines the cache size in conjunction with the M bit.
The M bit is 0 for DCache and ICache.
The size field is bits [21:18] for the DCache and bits [9:6] for the ICache.
The minimum size of each cache is 4 KB; the maximum size is 128 KB.
Cache size encoding with M=0:
Size field Cache size
0b0011 4 KB
0b0100 8 KB
Note: The NS9750 always reports 4KB for DCache and 8KB for ICache.
Assoc Determines the cache associativity in conjunction with the M bit.
The M bit is 0 for both DCache and ICache.
The assoc field is bits [17:15 for the DCache and bits [5:3] for the ICache.
Cache associativity with encoding:
Assoc field Associativity
0b010 4-way
Other values Reserved
M bit Multiplier bit. Determines the cache size and cache associativity values in conjunction with the
size and assoc fields.
Note: This field must be set to 0 for the ARM926EJ-S processor.
Len Determines the line length of the cache.
The len field is bits [13:12] for the DCache and bits [1:0] for the ICache.
Line length encoding:
Len field Cache line length
10 8 words (32 bytes)
Other values Reserved
11 10 9 6 5 3 2 1 0
0 0 Size M Assoc Len