Digi NS9750 User Manual
Page 232
R e g i s t e r s
2 0 8
N S 9 7 5 0 H a r d w a r e R e f e r e n c e
The Configuration register configures memory controller operation. It is
recommended that this register be modified during system initialization, or when
there are no current or outstanding transactions. Wait until the memory controller is
idle, then enter low-power or disabled mode.
Register bit assignment
Dynamic Memory Control register
Address: A070 0020
Bits
Access
Mnemonic
Description
D31:09
N/A
Reserved
N/A (do not modify)
D08
R/W
CLK
Clock ratio (HCLK:clk-out[3:0]) ratio
0
1:1 (reset value on
reset_n
)
1
1:2
D07:01
N/A
Reserved
N/A (do not modify)
D00
R/W
END
Endian mode
0
Little endian mode
1
Big endian mode
The value of the endian bit on power-on reset (
reset_n
) is determined
by the
gpio[44]
signal. This value can be overridden by software. This
field is not affected by the AHB reset (
HRESETn
).
Note:
The value of the
gpio[44]
signal is reflected in this field.
When programmed, this register reflects the last value
written into the register. You must flush all data in the
memory controller before switching between little endian
and big endian modes.
Table 140: Configuration register
END
13
12
11
10
9
8
7
6
5
4
3
2
1
0
15
14
31
29
28
27
26
25
24
23
22
21
20
19
18
17
16
30
Reserved
Reserved
CLK
Reserved