Core phase (ieee1284) register, Register bit assignment – Digi NS9750 User Manual
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B B u s s l a v e a n d D M A i n t e r f a c e
7 0 4
N S 9 7 5 0 H a r d w a r e R e f e r e n c e
Core Phase (IEEE1284) register
Address: 9040 0178
Register bit assignment
Bits
Access
Mnemonic
Reset
Description
D31:08
R
Reserved
0x0
N/A
D07:00
R
pha
0x0
0x00spp forward idle
0x01
spp forward data transfer
0x0f
spp reset
0x14
negotiate phase
0x18
terminate phase
0x24
nibble/byte reverse idle
0x26
nibble/byte reverse data transfer (see Warning
below)
0x28
nibble/byte host busy data not available
0x2C
nibble/byte host busy data available
0x2E
nibble/byte host interrupt
0x30
ecp forward idle
0x31
ecp forward data transfer
0x34
ecp reverse idle
0x36
ecp reverse data transfer
0x38
ecp host recovery
0x3C
ecp reverse to forward phase transition
0x3E
ecp forward to reverse phase transition
0x3F
ecp setup phase
Table 413: Core Phase register
pha
13
12
11
10
9
8
7
6
5
4
3
2
1
0
15
14
31
29
28
27
26
25
24
23
22
21
20
19
18
17
16
30
Reserved
Reserved