Digi NS9750 - Manual (Page 875)

I - I n d e x - 5
R3, Domain Access Control
register
61
,
98
R4 register 62
R5, Fault Status registers 62
R6, Fault Address register 64 , 97
R7, Cache Operations register 64 - 68
R8, TLB Operations register
68
R9, Cache Lockdown register 69 - 73
system control processor
registers 51 - 77
addresses 51
summary
53
terms and abbreviations
52
CPU arbiter, high speed 255
CPU bus arbitration 472
CPU subsystem 255
cross-bridge transaction error
handling
407
D
data and command FIFOs 675
data structures in LCD panels 570 - 572
DC electrical characteristics 790 - 791
inputs
790
outputs 791
DC electrical inputs, USB 790
DC electrical outputs, USB 791
DCache, data cache 56 , 67 , 68 , 105 , 106 ,
107
,
108
write buffer 106
debug mode (GPTC) 264
decoding. See BBus peripheral address
map.
destination address
475
,
505
device block, USB
708
,
709
,
710
-
712
architecture 710
control and status 710
logical and physical endpoints 712
packet and data flow
711
Device Control and Status register
718
Device IP Programming Control/Status
register 724
device selection for configuration,
PCI
458
DMA
BBus controller. See BBus DMA
controller.
descriptor list processing 476
DMA accesses, BBus bridge
471
memory-to-peripheral transfers 471
peripheral-to-memory transfers 471
DMA buffer descriptor 474 , 504 - 508
buffer length 505
definition
505
destination address
505
DMA transfer status 506 - 508
FULL bit 506
illustration 505
interrupt bit 506
LAST bit
506
source address 505
status field 506
WRAP bit 505
DMA Buffer Descriptor Pointer
register
512
DMA Channel 1/2 Control register
491
DMA channel assignments 509 - 510
DMA context memory 503
DMA Control register 514
DMA controller
two-channel
468
,
474
-
483
initiating a DMA transfer 474
DMA memory-to-peripheral transfers 471
DMA Peripheral Chip Select register 496
DMA peripheral-to-memory transfers 471