Digi NS9750 - Manual (Page 560)

B B u s U t i l i t y C o n t r o l a n d S t a t u s r e g i s t e r s
5 3 6 N S 9 7 5 0 H a r d w a r e R e f e r e n c e
BBus DMA Interrupt Status register
Address: 9060 0060
The BBus DMA Interrupt Status register contains the interrupt status bits for the BBus
DMA Controller. The interrupt bits are active high. Service these interrupts in the
BBus DMA controller.
Register bit assignment
Bits Access Mnemonic Reset Description
D31:16 R Not used 0x0 Always read as 0x0
D15 R BINT16 0 BBus DMA channel #16 interrupt status
D14 R BINT15 0 BBus DMA channel #15 interrupt status
D13 R BINT14 0 BBus DMA channel #14 interrupt status
D12 R BINT13 0 BBus DMA channel #13 interrupt status
D11 R BINT12 0 BBus DMA channel #12 interrupt status
D10 R BINT11 0 BBus DMA channel #11 interrupt status
D09 R BINT10 0 BBus DMA channel #10 interrupt status
D08 R BINT9 0 BBus DMA channel #9 interrupt status
D07 R BINT8 0 BBus DMA channel #8 interrupt status
D06 R BINT7 0 BBus DMA channel #7 interrupt status
D05 R BINT6 0 BBus DMA channel #6 interrupt status
D04 R BINT5 0 BBus DMA channel #5 interrupt status
D03 R BINT4 0 BBus DMA channel #4 interrupt status
Table 329: BBus DMA Interrupt Status register
BINT
14
13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14
31 29 28 27 26 25 24 23 22 21 20 19 18 17 16 30
Not used
BINT
16
BINT
15
BINT
13
BINT
12
BINT
11
BINT
10
BINT
9
BINT
8
BINT
7
BINT
6
BINT
5
BINT
4
BINT
3
BINT
2
BINT
1