Digi NS9750 - Manual (Page 435)

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P C I - t o - A H B B r i d g e
Endian configuration
The PCI bus is defined as little endian and the AHB bus can be defined as either Big or
little endian. The PCI-to-AHB bridge supports byte-swapping only when the AHB bus is
configured as a big endian bus. Byte-swapping is selected using the endian mode bit
in the Miscellaneous System Configuration register (see "Miscellaneous System
Configuration and Status register," beginning on page 296). Table 252 shows the byte-
swapping scheme used.
Configuration registers
The Configuration registers within the PCI-to-AHB bridge are accessed using PCI
configuration cycles. Two registers are used to access the configuration registers from
the AHB side: Configuration Address Port (
CONFIG_ADDR
) and Configuration Address
Data Port (
CONFIG_DATA
).
Table 253 describes the fields in the Configuration Address Port register. The
Configuration Address Data Port register has no specific format; it contains the read
or write configuration data.
PCI bus byte AHB bus byte
Data[31:24] AHB_Data[7:0]
Data[23:16] AHB_Data[15:8]
Data[15:08] AHB_Data[23:16]
Data[07:00] AHB_Data[31:24]
Table 252: Big endian byte-swapping
Bits Access Mnemonic Reset Description
D31 R/W ENABLE 0x0 Enable translation
0 Disabled (default)
1 Enabled
Enables translation of a subsequent access to the
CONFIG_DATA register to a PCI configuration
cycle.
D30:24 N/A Reserved N/A N/A
Table 253: CONFIG_ADDR register