Digi NS9750 - Manual (Page 853)

w w w . d i g i e m b e d d e d . c o m 8 2 9
T i m i n g
6 C
load
= 10pf for all outputs.
7 SPI data order can be reversed such that LSB is first. Use the BITORDR bit in Serial Channel
B/A/C/D Control Register A.
SPI master mode 0 and 1: 2-byte transfer
(see note 7)
Figure 136: SPI master mode 0 and 1 (2-byte transfer)
SPI master mode 2 and 3: 2-byte transfer
(see note 7)
Figure 137: SPI master mode 2 and 3 (2-byte transfer)
MSB LSB MSB LSB
MSB LSB MSB LSB
SP6 SP4
SP8 SP7
S10 SP5 SP1
S9 SP12 SP12
SP11 SP11
SP13 SP13 SP3 SP0
SPI CLK Out (Mode 0)
SPI CLK Out (Mode 1)
SPI Enable
SPI Data Out
SPI Data In
MSB LSB MSB LSB
MSB LSB MSB LSB
SP6 SP4
SP8 SP7
S10 SP5 SP1
S9 SP3 SP0
SPI CLK Out (Mode 2)
SPI CLK Out (Mode 3)
SPI Enable
SPI Data Out
SPI Data In