Digi NS9750 User Manual
Page 441
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P C I - t o - A H B B r i d g e
PCI BIST register
Read-only value, hardwired to
0x0
.
PCI Base Address registers [5:0]
The PCI-to-AHB bridge supports the six Base Address registers defined by PCI.
Table 257 defines the memory space size decoded by each register.
Each Base Address register is enabled using the
ENBAR0–ENBAR5
bits in the PCI
Miscellaneous Support register (see page 426) in the PCI arbiter. Note that the bridge
forces the four least significant bits (LSBs) of each Base Address register to
0x0
. As
such, PCI defines each register with the following characteristics:
Memory space indicator
Located anywhere in the 32-bit address space
Not prefetchable
PCI CardBus CIS Pointer register
Read-only value, hardwired to
0x0
.
PCI Subsystem Vendor ID register
Read-only value. To change this value, use the
SUBVENDOR_ID
field in the PCI
Configuration 2 register (see page 430) in the PCI arbiter.
Base Address register
Memory size decoded
0
256 MB
1
64 MB
2
16 MB
3
4 MB
4
1 MB
5
256 KB
Table 257: Base Address register decoding sizes