Pci bridge interrupt status register, Register bit assignment, Table 270: pci bridge pci error address register – Digi NS9750 User Manual
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P C I b u s a r b i t e r
4 3 4
N S 9 7 5 0 H a r d w a r e R e f e r e n c e
The PCI Bridge PCI Error Address register stores the address of the PCI transaction
that received a PCI bus error response.
Register bit assignment
PCI Bridge Interrupt Status register
Address: A030 002C
The PCI Bridge Interrupt Status register shows the status of the AHB bus error
interrupt.
Bits
Access
Mnemonic
Reset
Description
D31:00
R
PCIEADR
0x00000000
PCI error address
Holds the PCI address that caused an error, when any
of the PCI error bits are set in the PCI Status register.
No further updates are allowed to this register until all
error bits are cleared.
Table 270: PCI Bridge PCI Error Address register
PCIEADR
13
12
11
10
9
8
7
6
5
4
3
2
1
0
15
14
31
29
28
27
26
25
24
23
22
21
20
19
18
17
16
30
PCIEADR
Reserved
13
12
11
10
9
8
7
6
5
4
3
2
1
0
15
14
31
29
28
27
26
25
24
23
22
21
20
19
18
17
16
30
Reserved
AHB
ERR