Ethernet general control register #2, Register bit assignment, Table 206: ethernet general control register #1 – Digi NS9750 User Manual
Page 366: Table 207: ethernet general control register #2
E t h e r n e t C o n t r o l a n d S t a t u s r e g i s t e r s
3 4 2
N S 9 7 5 0 H a r d w a r e R e f e r e n c e
Ethernet General Control Register #2
Address: A060 0004
Register bit assignment
D08
R/W
ITXA
0
Insert transmit source address
0
Source address for Ethernet transmit frame taken
from data in TX_FIFO.
1
Insert the MAC Ethernet source address into the
Ethernet transmit frame source address field.
Set to force the MAC to automatically insert the Ethernet
MAC source address into the Ethernet transmit frame
source address. The SA1, SA2, and SA3 registers provide
the address information. When the ITXA bit is cleared, the
Ethernet MAC source address is taken from the data in the
TX_FIFO.
D07:00
N/A
Reserved
N/A
N/A
Bits
Access
Mnemonic
Reset
Description
Table 206: Ethernet General Control Register #1
Bits
Access
Mnemonic
Reset
Description
D31:04
R/W
Not used
0
Always write as 0.
Table 207: Ethernet General Control Register #2
Not used
T
CLER
STEN
13
12
11
10
9
8
7
6
5
4
3
2
1
0
15
14
31
29
28
27
26
25
24
23
22
21
20
19
18
17
16
30
Not used
AUTO
Z
CLR
CNT