Digi NS9750 - Manual (Page 388)

E t h e r n e t C o n t r o l a n d S t a t u s r e g i s t e r s
3 6 4 N S 9 7 5 0 H a r d w a r e R e f e r e n c e
Register bit assignment
Station Address registers
Address: A060 0440 / 0444 / 0448
The 48-bit station address is loaded into Station Address Register #1, Station Address
Register #2, and Station Address Register #3, for use by the station address logic (see
"Station address logic (SAL)" on page 321).
Bits Access Mnemonic Reset Description
D31:04 N/A Reserved N/A N/A
D03 R MIILF 0 MII link failure
When set to 1, indicates that the PHY currently has a
link fail condition.
D02 R NVALID 0 Read data not valid
When set to 1, indicates that the MII Management
read cycle has not completed and the read data is not
yet valid. Also indicates that SCAN READ is not
valid for automatic scan reads.
D01 R SCAN 0 Automatically scan for read data in progress
When set to 1, indicates that continuous MII
Management scanning read operations are in
progress.
D00 R BUSY 0 MII interface BUSY with read/write operation
When set to 1, indicates that the MII Management
module currently is performing an MII Management
read or write cycle. This bit returns to 0 when the
operation is complete.
Table 223: MII Management Indicators register
Reserved
OCTET1
13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14
31 29 28 27 26 25 24 23 22 21 20 19 18 17 16 30
OCTET2