Digi NS9750 - Manual (Page 354)

E t h e r n e t f r o n t - e n d m o d u l e
3 3 0 N S 9 7 5 0 H a r d w a r e R e f e r e n c e
contain the correct value. In this situation, software must keep track of the
location of the next buffer descriptor to be kicked off.
If the
TX_WR
logic detects that the frame was aborted or had an error, the
logic updates the current buffer descriptor as described in the previous
paragraph. If the frame was aborted before the last buffer descriptor of the
frame was accessed, the result is a situation in which the status field of a
buffer descriptor, which is not the last buffer descriptor in a frame, has a
non-zero value. The
TX_WR
logic stops processing frames until
TCLER
(clear
transmit logic) in Ethernet General Control Register #2 is toggled from low
to high to resume processing. The
TX_WR
logic also sets
TXERR
(last frame
not transmitted successfully) in the Ethernet Interrupt Status register and
loads the TX buffer descriptor RAM address of the current buffer descriptor
in the TX Error Buffer Descriptor Pointer register (see page 390). This allows
identification of the frame that was not transmitted successfully. As part of
the recovery procedure, software must read the TX Error Buffer Descriptor
Pointer register and then write the 8-bit address of the buffer descriptor to
resume transmission into the Transmit Recover Buffer Descriptor Pointer
register.
Transmitting a frame to the Ethernet MAC
The
TX_RD
logic is responsible for reading data from the TX_FIFO and sending it to the
Ethernet MAC. The logic does not begin reading a new frame until the TX_FIFO is full.
This scheme decouples the data transfer to the Ethernet MAC from the fill rate from
the AHB bus. For short frames that are less than 256 bytes, the transmit process
begins when the end-of-frame signal is received from the
TX_WR
logic.
When the MAC completes a frame transmission, it returns status bits that are stored
in the Ethernet Transmit Status register (see page 344) and written into the status
field of the current buffer descriptor.
Ethernet Slave Interface
The AHB slave interface supports only single 32-bit transfers. The slave interface also
supports limiting CSR and RAM accesses to CPU “privileged mode” accesses. Use the
internal register access mode
bit 0 in the Miscellaneous System Configuration register to set
access accordingly (see "Miscellaneous System Configuration and Status register,"
beginning on page 296).