Digi NS9750 User Manual
Page 439
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P C I - t o - A H B B r i d g e
PCI Status register
Table 256 describes the PCI Status register fields.
Bits
Access
Mnemonic
Reset
Description
D15
R/C
DPE
0
Detected parity error
Device detected parity error. Used as an interrupt source
to AHB bus.
D14
R/C
SERR#
0
Signaled system error
Device generated system error (SERR#). Used as an
interrupt source to AHB bus.
D13
R/C
RMA
0
Received master abort
Master aborted transaction. Used as an interrupt source
to AHB bus.
D12
R/C
RTA
0
Received target abort
Master received target abort. Used as an interrupt source
to AHB bus.
D11
R/C
STA
0
Signaled target abort
Master signaled the target abort as target. Used as an
interrupt source to AHB bus.
D10:09
Hard-wired
to 10
DEVSEL
10
DEVSEL timing for target
00
Fast
01
Medium
10
Slow
11
Reserved
D08
R/C
PERR#
0
Master data parity error
The master detected a parity error and the following
conditions exist:
Master initiated transaction
Master set PERR# (read) or detected PERR#
asserted by target (write)
Parity error response bit set in the PCI Command
register
Used as an interrupt source to the AHB bus.
Table 256: PCI Status register