Digi NS9750 - Manual (Page 712)

B B u s s l a v e a n d D M A i n t e r f a c e
6 8 8 N S 9 7 5 0 H a r d w a r e R e f e r e n c e
Register bit assignment
Bits Access Mnemonic Reset Description
D31:00 W RvFifoWriteReg N/A Write one to four bytes to the Reverse FIFO
when in CPU mode.
A FIFO entry containing one byte or two
bytes is written to Reverse FIFO Write
Register — Last.
A FIFO entry containing three bytes is
written in two steps:
Step 1: The lowest 16 bits are written to
the Reverse FIFO Register.
Step 2: The high byte is written to the
Reverse FIFO Write Register — Last.
A FIFO entry containing four bytes is
written to either register.
D31:00 W RvFifoWrite
Reg — Last N/A
Table 396: Reverse Data FIFO Write register/Reverse Data FIFO Write Register — Last
13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14
31 29 28 27 26 25 24 23 22 21 20 19 18 17 16 30
RvFifoWriteReg - Last
RvFifoWriteReg - Last