Digi NS9750 User Manual
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M e m o r y C o n t r o l l e r
Static Memory Page Mode Read Delay 0–3 registers
Address: A070 0210 / 0230 / 0250 / 0270
The Static Memory Page Mode Read Delay 0–3 registers allow you to program the
delay for asynchronous page mode sequential accesses. These registers control the
overall period for the read cycle. It is recommended that these registers be modified
during system initialization, or when there are no current or outstanding
transactions. Wait until the memory controller is idle, then enter low-power or
disabled mode.
Register bit assignment
Bits
Access
Mnemonic
Description
D31:05
N/A
Reserved
N/A (do not modify)
D04:00
R/W
WTPG
Asynchronous page mode read after the first wait state
(WAITPAGE)
00000–11110
(n+1) HCLK cycle for read access time. For
asynchronous page mode read for sequential reads, the
wait state time for page mode accesses after the first read
is (WAITPAGE+1) x t
HCLK
11111
32 HCLK cycles read access time (reset value on
reset_n
)
Number of wait states for asynchronous page mode read accesses
after the first read.
Table 163: Static Memory Page Mode Read Delay 0–3 registers
13
12
11
10
9
8
7
6
5
4
3
2
1
0
15
14
31
29
28
27
26
25
24
23
22
21
20
19
18
17
16
30
Reserved
Reserved
WTPG