Digi NS9750 - Manual (Page 744)

U S B G l o b a l r e g i s t e r s
7 2 0 N S 9 7 5 0 H a r d w a r e R e f e r e n c e
Global Interrupt Enable register
Address: 9010 000C
The Global Interrupt Enable register contains the global interrupt enable
information. All interrupts are enabled by writing a 1 and disabled by writing a 0.
Register bit assignment
Bits Access Mnemonic Reset Description
D31 R/W GBL_EN 0 Global interrupt enable
Enables all interrupts.
For normal operation, this field should be written to 1.
D30:28 R/W Not used 0 Always write to 0.
D27 R/W GBL_DMA 0 Global DMA interrupt enable
Enables all DMA-generated interrupts.
For normal operation, this field should be written to 1.
D26 R/W DMA13 0 DMA channel 13 interrupt
D25 R/W DMA12 0 DMA channel 12 interrupt
D24 R/W DMA11 0 DMA channel 11 interrupt
D23 R/W DMA10 0 DMA channel 10 interrupt
D22 R/W DMA9 0 DMA channel 9 interrupt
D21 R/W DMA8 0 DMA channel 8 interrupt
D20 R/W DMA7 0 DMA channel 7 interrupt
D19 R/W DMA6 0 DMA channel 6 interrupt
D18 R/W DMA5 0 DMA channel 5 interrupt
Table 419: Global Interrupt Enable register
Not
used
FIFO SOF URST SSPND
SET
INTF
SET
CFG
WAKE
UP
Not used
OHCI_
IRQ
Not
used
13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14
DMA
2
DMA
1
31 29 28 27 26 25 24 23 22 21 20 19 18 17 16 30
Not used
DMA
13
GBL_
DMA
DMA
12
DMA
11
DMA
10
DMA
9
DMA
8
DMA
7
DMA
6
DMA
5
DMA
4
DMA
3
GLB_
EN