Digi NS9750 - Manual (Page 226)

R e g i s t e r s
2 0 2 N S 9 7 5 0 H a r d w a r e R e f e r e n c e
Registers
The external memory is accessed using the AHB memory interface ports. Addresses
are not fixed, but are determined by the AHB decoder and can be different for any
particular system implementation. Transfers to the external memory controller
memories are selected by the
HSELMPMC[3:0]CS[7:0]
signals (where [3:0] indicates the
AHB port number and [7:0] indicates the chip select to be accessed.)
Register map
Table 137 lists the registers in the Memory Controller register map.
All configuration registers must be accessed as 32-bit words and as single accesses
only. Bursting is not allowed.
Address Register Description
A070 0000 Control register Control register
A070 0004 Status register Status register
A070 0008 Config register Configuration register
A070 0020 DynamicControl Dynamic Memory Control register
A070 0024 DynamicRefresh Dynamic Memory Refresh Timer
A070 0028 DynamicReadConfig Dynamic Memory Read Configuration register
A070 0030 DynamictRP Dynamic Memory Precharge Command Period (t
RP
)
A070 0034 DynamictRAS Dynamic Memory Active to Precharge Command
Period (t
RAS
)
A070 0038 DynamictSREX Dynamic Memory Self-Refresh Exit Time (t
SREX
)
A070 003C DynamictAPR Dynamic Memory Last Data Out to Active Time
(t
APR
)
A070 0040 DynamictDAL Dynamic Memory Data-in to Active Command Time
(t
DAL
or T
APW
)
A070 0044 DynamictWR Dynamic Memory Write Recovery Time (t
WR
, t
DPL
,
t
RWL
, t
RDL
)
Table 137: Memory Controller register map